1. Field of the Invention
The present invention generally relates to phase-locked loops (PLLs). More particularly, the present invention relates to methods and apparatus for altering terminal counts of PLLs without re-programming.
2. Description of the Related Art
Conventional PLLs typically include a voltage controlled oscillator (VCO) that generates an output signal. This output signal is compared with a reference signal in a feedback loop to control the VCO. In this manner, PLLs can generate an output signal based on a reference signal.
Conventional PLLs can also include frequency dividers to produce output signals that are multiples of the reference signals. The modulus of the frequency dividers determines the multiplication of the reference signals. For example, a frequency divider with a modulus of 2 can produce an output signal that is twice as large in frequency as the reference signal.
In some applications, such as in generating radio signals, dual-modulus prescaling can be used rather than a single variable division. In contrast to the example given above, in dual-modulus prescaling, the output signal is divided by two different moduli.
More particularly, conventional PLLs with dual-modulus prescaling typically have a main counter and an auxiliary counter. These counters are configured such that the main counter has a longer count than the auxiliary counter. During the time that both the main counter and the auxiliary counters are counting, the output signal is divided by one modulus. When the auxiliary counter stops counting and until the main counter stops counting, the output signal is divided by another modulus. Thus, the frequency of the output signal is determined in part by the number of counts of the main and auxiliary counters.
In conventional PLLs with dual-modulus prescaling, the number of counts of the main and auxiliary counters is re-programmed in order to change the frequency of the output signal. However, re-programming the main and auxiliary counters can be time consuming and result in undesirable delay. Moreover, this delay can be unacceptable in applications that require rapid changes in the output signal.
The present invention relates to altering terminal counts of phase-locked loops (PLLs) without re-programming. In one embodiment of the present invention, a PLL includes a down counter having a detection circuit configured to determine when the counter reaches its terminal count. In accordance with one aspect of the present invention, the down counter also includes a control line configured to alter the terminal count detected by the detection circuit by an off-set.